Skip to main content Skip to table of contents. This service is more advanced with JavaScript available. Encyclopedia of Nanotechnology Edition. Editors: Bharat Bhushan. Contents Search. MEMS Packaging. How to cite. Synonyms MEMS encapsulation. To ensure proper operation in environments that may be encountered, This is a preview of subscription content, log in to check access. Dokmeci, M.
Gooch, R. A 17 4 , — Google Scholar. Kim, B. Accessed 29 Mar DeNatale, J. This mechanical part must be protected during the packaging and handling process. Moreover, vacuum encapsulation may be required for these microstructures in applications such as resonant accelerometers [ A "packaging cap" with properly designed micro cavity is to be fabricated to encapsulate and protect the fragile MEMS structure as the first-level MEMS post-packaging process.
The wafer can be diced afterward, and the well-established packaging technology in IC industry can follow and finish the final packaging step. Unlike the packaging requirements for ICs, however, the common MEMS packaging requirement is hermetic seal and sometimes vacuum encapsulations.
Hermetic seal is important to ensure that no moisture or contaminant can enter the package. This increases the difficulty of common IC packaging processes tremendously. Although most single function MEMS chips can employ typical IC packaging techniques, such as die-attached processes, wiring interconnects, molded plastic, ceramic, and metal for packaging [ Before the state-of-the-art MEMS packaging processes are discussed, several primary micro-fabrication processes for packaging applications are described.
Other silicon-based processes, such as thin-film deposition , wet and dry chemical etching, lithography, lift-off, and wiring bonding processes can be found in many textbooks [ This technique is commonly used in the assembly process between a chip with microelectronics and a package substrate [ The microelectronic chip is "flipped joined" with the packaging substrate, and metal solder bumps are used as both the bonding agents and electrical paths between bond pads on the microelectronic chip and metal pads on the package substrate.
In the FC technique, solder bumps are generally fabricated by means of electroplating. This technology is very similar to the FC technique. An area array of solder balls on a single chip module or multi-chip module are used in the packaging process as electrical, thermal, and mechanical connects to join the module with the next level package, usually a printed circuit board [ This is a chemical etching process to make through-wafer channels on a silicon substrate for the fabrication of vertical through-wafer interconnects.
The chemical etching process can be either wet or dry.
0コメント